The present invention relates generally to CMOS integrated circuits, and more particularly, to CMOS circuit techniques for interfacing from static single-ended logic to differential dynamic logic.
Static logic gates have been utilized to construct logic circuits for performing mathematical operations. Static logic gates are those which can continuously perform logic operations so long as electrical power is available. In other words, static logic gates need no electrical precharge, or refresh, in order to properly perform logic operations. However, static logic gates are undesirably slow individually and, when chained together to collectively perform a logic function, are even slower.
Dynamic logic gates are used in the design of logic circuits which require high performance and modest size. Dynamic logic gates are those which require a periodic electrical precharge, or refresh, such as with a dynamic random access memory (RAM), in order to maintain and properly perform its intended logic function. Once an electrical precharge supplied to a dynamic logic gate has been discharged by the dynamic logic gate, the dynamic logic gate can no longer perform another logic function until subsequently precharged. Accordingly, dynamic logic usually has at least two clock phases. One clock phase is called the precharge phase. During the precharge phase, the electrical precharge is supplied to the dynamic logic gates. A second clock phase is called the evaluate phase. During the evaluate phase, the electrical precharges of the dynamic logic gates may be discharged depending upon the inputs to the dynamic logic gates.
It is often desireable to mix static and dynamic logic circuits on the same integrated circuit. This allows the designer to pick the appropriate type of logic depending upon a variety of factors including speed, power dissipation, simplicity, cost, and ease of use.
Unfortunately, a typical requirement of dynamic logic is that the inputs to a dynamic gate either remain stable during the entire evaluate phase ,or that the inputs are monotonic. That means that only one transition from a predetermined logic level to the other one may occur without causing problems. Typically, the allowed transition is a single low to high transition. However, static logic may transition in either direction, multiple times, during a clock cycle. Therefore, signals driven by static logic should not be used as inputs to dynamic logic. This presents a problem for integrated circuits that want to mix static and dynamic logic circuits.
Accordingly, there is a need in the art for a circuit that interfaces static logic to dynamic logic. It is desirable that such a circuit use clocks that are standard to both the static and dynamic circuits. This simplifies design. Likewise, to simplify design, such a circuit should use standard circuit elements.
In a preferred embodiment, the invention provides a static logic signal to dynamic logic interface that produces a monotonic output. The invention is fast because it does not introduce a xe2x80x9cdeadxe2x80x9d gate delay where no useful logic function is performed into the evaluation phase of the dynamic logic. The invention does not require the generation of special clocks that can create setup and hold time problems. Finally, the invention may be constructed using standard CMOS integrated circuit building blocks which simplifies design and implementation.
An embodiment of the invention uses standard clock signals, a delay element that can be as simple as a series of inverters, and an enabled latch to interface static logic to dynamic logic. The inverse of the dynamic logic evaluate clock is fed to the clock input of a transparent latch with clock and enable inputs. A delayed version of this clock is generated by the delay element. This delayed inverse of the dynamic logic evaluate clock is fed to the enable input of the latch. The input to the latch comes from static logic and the output of the latch is fed to the dynamic logic. The net result is a latch that is open until the evaluate clock is instructing the dynamic logic to evaluate and remains closed until a delay element delay time after the evaluate clock instructs the dynamic logic to reset.